The invention relates to a circuit arrangement for switching high-voltage signals by means of low-voltage signals, particularly for driving a semiconductor memory arrangement and to a method for switching high-voltage signals by means of low-voltage signals, particularly for driving a semiconductor memory arrangement.
EEPROMs (Electrically Erasable Programmable Read Only Memories) or EAROMs (Electrically Alterable ROM), so-called flash memories, are known in various embodiments from the prior art. EEPROM/flash memories are generally divided into rows, so-called word lines, and columns, so-called bit lines, each intersection of bit lines and word lines representing one memory cell.
FIG. 7 shows a circuit diagram of a section from a cell array 1, comprising two word lines WLn, WLn−1, and two bit lines BLm, BLm+1′ of an electrically erasable and then reprogrammable read only memory (EEPROM) according to the prior art.
Each intersection of a word line WLn, WLn−1 with a bit line BLm, BLm+1 comprises a memory cell 2 as shown, for example, in FIG. 8.
Each memory cell 2 comprises two transistors, namely a cell transistor 4 and a select transistor 3, the drain of the cell transistor 4 being connected to the source of the select transistor 3. Whereas the select transistor 3 is a conventional NMOS transistor of the enhancement type, the NMOS cell transistor has an electrically variable threshold voltage Uth. For this purpose, the cell transistor 4 comprises a so-called tunnel window 5 via which charges for changing the threshold voltage Uth can be supplied to a floating gate FG4 of the cell transistor 4.
Each word line WLn, WLn−1 comprises two control lines, namely a drive line CGLn, CGLn−1 for the so-called control gates CG4 of the respective cell transistors 4 of a respective word line WLn, WLn−1, and a drive line SGLn, SGLn−1 for the so-called select gates SG3 of a respective select transistor 3 of a respective word line WLn, WLn−1.
Each bit line BLm, BLm+1 likewise comprises two control lines, namely a drive line Sm, Sm+1 for the sources S4 of the respective cell transistors 4 of a respective bit line BLm, BLm+1, and a drive line Dm, Dm+1 for the respective drains D3 of the respective select transistors 3 of a respective bit line BLm, BLm+1.
Each memory cell can be selected by a suitable drive via the corresponding four associated drive lines. For example, the memory cell 2 in FIG. 7 can be driven via a corresponding circuit of the drive lines CGLn, SGLn of the n-th word line WLn and the drive lines Sm+1, Dm+1 of the m+1-th bit line BLm+1.
Each selected memory cell can be operated in three operating modes, namely the read mode, the erase mode and the program mode.
In the read mode, a memory cell is selected by applying a positive voltage of, for example, +1.8 volt to the select gate of the select transistor. The read mode results from the voltages applied to the source of the cell transistor, to the drain of the select transistor and to the control gate of the cell transistor of, in the exemplary embodiment, 1.2 volt, 0 volt and 1.8 volt.
In the erase mode, a memory cell is selected by applying a high positive voltage of in this case 18 volts to the control gate of the cell transistor.
Selection in the program mode occurs by applying 0 volt to the source of the cell transistor, −8.4 volts to the control gate of the cell transistor, +10 volts to the select gate of the select transistor and +6.6 volts to the drain of the select transistor. This circuit application simultaneously specifies the program mode.
All of the operating states can be seen in the table representation according to FIG. 9.
In FIG. 7, the voltage values in each case associated with the corresponding read mode (top), erase mode (in the center), program mode (bottom) are specified above the respective drive lines CGLn, SGLn, SGLn−1, CGLn−1, Sm, Dm, Sm+1, Dm+1. The values specified result in the memory cell identified by the reference symbol 2 being exclusively selected in all operating modes.
From the prior art, a multiplicity of circuit arrangements for driving the control gates of the cell transistors and the select gates of the select transistors with the voltages with relatively high values in the erase and program mode are known. A comparatively elaborate circuit arrangement is known, for example, from U.S. Pat. No. 5,265,052. A simpler circuit arrangement is described in the documents JP 06338197 A and DE 197 14 658 C2.
The drive to the select gates and control gates of the cell and select transistors, respectively, in a cell array with the aid of the circuit arrangements described in the two last-mentioned documents will firstly be described by means of drawing FIGS. 3 and 6.
FIG. 3 shows a circuit arrangement of a control gate driver 7 according to the prior art for driving the control gate CG4 of a cell transistor 4 and a corresponding drive line CGL. The control gate driver 7 according to the prior art consists of a low-voltage logic with low-voltage transistors 16 and a high-voltage unit with high-voltage transistors 15. The low-voltage section with the low-voltage transistors 16 comprises a word line decoder 10 and a low-voltage read driver 9.
The high-voltage section with the high-voltage transistors 15 consists of a high-voltage decoupling transistor 8 and a high-voltage latch 6. The HV decoupling transistor 8, in this case an NMOS transistor, comprises a gate G8, via which the high-voltage latch 6 can be separated from the low-voltage read driver 9. The high-voltage latch 6 consists of two series-connected inverters I1, I2, which in each case exhibit a PMOS transistor MP1, MP2 and an NMOS transistor MN1, MN2, the output of the second inverter I2, forming the output of the latch 6, being fed back to the input of the first inverter I1 via a feedback line RL. The source terminals of the respective transistors MP1, MP2 and, respectively, MN1, MN2, are in each case connected to one another via corresponding circuit nodes KP1 and KN1, respectively, and connected to a corresponding positive high-voltage supply HVP and negative high-voltage supply HVN, respectively.
Although the fundamental operation of the circuit arrangement is described in DE 197 14 658 C2, the operation of the control gate driver 7 will be explained by means of table 1 specified below.
TABLE 1notV(CON)V(HVP)V(HVN)selectedselectedErasevboost→0 Vvread→vpp0 V01Programvboost→vread→0 V0 V→10vprognvprognReadvboostvread0 V11The Read ModeThe Read Mode is Initiated as Follows:
The voltage vboost is present at the terminal CON, the voltage vread is present at terminal HVP and the terminal HVN is at 0 volt. This state is retained for as long as it is intended to read from the cell.
Erase Mode
The Erase Mode is Initiated as Follows:
Before erasing, vboost is present at the terminal CON, vread is present at the terminal HVP and 0 volt is present at terminal HVN. The HV latch is brought into the desired state by the low-voltage logic 10 via the low-voltage driver 9. Then the connection from the HV latch 7 to the NV driver 9 is separated by lowering the voltage at the gate terminal CON to HVN=0 volt. After that, the voltage at the positive high-voltage supply HVP is ramped up to the erase voltage vpp. After the erase time has elapsed, the voltage at terminal HVP is lowered back to the read voltage vread and the connection to the NV driver 9 is restored by raising the voltage at the gate terminal CON to the boost voltage vboost.
Program Mode
The Program Mode is Initiated as Follows:
Before programming, the boost voltage vboost is present at terminal CON, the read voltage vread is present at the high-voltage supply terminal HVP and 0 volt is present at the high-voltage supply terminal HVN. The high-voltage latch (HV latch) 7 is brought into the desired state by the low-voltage logic 10 via the low-voltage driver 9. Then the connection from the HV latch 7 to the NV driver 9 is separated by dropping the voltage at the control terminal CON to HVN=initially 0 volt. After that, the voltages at the negative high-voltage terminal HVN and at the control terminal CON are ramped to the negative programming voltage vprogn. After the programming time has elapsed, the voltage at terminal HVN is increased again to 0 volt. After that, the connection to the NV driver 9 is restored by ramping up the voltage at the terminal CON to the boost voltage vboost.
As can be seen from the above explanations, the control gate word line CGL in a flash EEPROM is operated    a) with low voltage levels (e.g. 0 volt and 2 volts) in the read mode,    b) with high voltage levels (e.g. 0 volt and 18 volts) in the erase mode,    c) with high voltage levels (e.g. −12 volts and 0 volt) in the program mode,the low-voltage logic section 16 having to be separated from the high-voltage section 15 in the erase and program mode.
To separate the low-voltage section 16 from the high-voltage section 15 and to reconnect them, the high-voltage transistor 8 is required which is driven with the so-called boost voltage vboost. To provide this boost voltage vboost requires a charge pump. For this charge pump, an area must be provided on the semiconductor chip and, as well, an operating current for operating this charge pump and a control logic are required. To switch from the disconnected state to the read mode, the charge pump requires a certain time until it has reached its maximum output voltage. The flash EEPROM can only be read out after this time has elapsed.
Similar disadvantages occur if the operation of a so-called select gate driver 17 according to the prior art is considered as is shown, for example, in FIG. 6.
FIG. 6 shows a circuit arrangement of a select gate driver 17 according to the prior art for driving the select gate SG4 of a cell transistor 4 and a corresponding drive line SGL. The select gate driver 17 according to the prior art consists of a low-voltage logic with low-voltage transistors 26, and a high-voltage unit with high-voltage transistors 25. The low-voltage section with the low-voltage transistors 26 comprises a word line decoder 20 and a low-voltage read driver 19.
The high-voltage section with the high-voltage transistors 25 consists of a high-voltage decoupling transistor 18 and a high-voltage latch 21. The HV decoupling transistor 18, again an NMOS transistor, comprises a gate G18 via which the high-voltage latch 21 can be separated from the low-voltage read driver 19. The high-voltage latch 21 consists of two series-connected inverters I1, I2, in each case exhibiting a PMOS transistor MP1, MP2, and an NMOS transistor MN1, MN2, the output of the second inverter I2 forming the output of the latch 21 being fed back to the input of the first inverter I1 via a feedback line RL. The source terminals of the respective transistors MP1, MP2 and, respectively, MN1, MN2 are in each case connected to one another via corresponding circuit nodes KP1 and KN1, respectively, and are connected to a corresponding positive high-voltage supply HVP and ground GND (terminal 22).
Although the fundamental operation of the circuit arrangement is described in DE 197 14 658 C2, the operation of the select gate driver 17 will be explained here, too, by means of the table 2 specified below.
TABLE 2Logic level at sgi  voltage at SGLnotV(CON)V(HVP)selectedselectedErasevboostvread1   vdd1   vddProgramvboost → 0 Vvread → vpp0   0 V1   vppReadvboostvread0   0 V1   vddThe Read ModeThe Read Mode is Initiated as Follows:
At terminal CON, the voltage vboost is present and at terminal HVP the read voltage vread is present. As long as no reading takes place, 0 volt are present at sgi and SGL. If it is intended to read from the relevant word line, the voltage at sgi is raised to the read voltage VRead for a short time by the NV driver and then lowered again to 0 volt. Via the low-resistance connecting transistor 18, the voltage at SGL follows the voltage at sgi.
Erase Mode
The Erase Mode is Initiated as Follows:
At terminal CON, the voltage vboost is present and at terminal HVP the voltage vread is present. The logic level is 1 and thus vread is also present at SGL. This state is retained as long as erasing is taking place.
Program Mode
The program mode is initiated as Follows:
Before programming, the boost voltage vboost is present at terminal CON and the read voltage vread is present at terminal HVP. The HV latch 17 is brought into the desired state by the low-voltage logic 20 via the low-voltage driver 19. Then the connection from the HV latch 17 to the NV driver 19 is separated by lowering the voltage at CON to 0 volt. After that, the voltage at HVP is ramped to the voltage vboost. After the programming time has elapsed, the voltage at HVP is dropped again to 0 volt. After that, the connection to the NV driver 19 is restored by ramping up the voltage at CON to vboost.
As can be seen from the above, the driving of a select gate word line SGL in an EEPROM is characterized by the fact that it is operated    a) very rapidly with low voltage levels (e.g. 0 volt and 2 volts) in a read mode, and    b) with high voltage levels (e.g. 0 volt and 10 volts) in a program mode,the low-voltage logic section 26 having to be separated from the high-voltage section 25 in the program mode.
If a high-voltage transistor 18 is used for separating the low-voltage logic and the read amplifier from the high-voltage latch 21, a so-called boost voltage vboost is again needed. To generate this voltage, a separate charge pump is again necessary.